1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel manufacturing process and device configuration for providing the split trench gates having reduced gate resistance Rg and different work functions of the top and bottom portions of the trench gate for more flexible performance and functional adjustments.
2. Description of the Prior Art
Conventional processes for manufacturing semiconductor power devices with metal gate are often limited by one drawback due to the dopant segregation during the gate oxide formation or subsequent thermal cycles in the manufacturing processes. Conventional power semiconductor devices are frequently manufactured by forming the body region first then forming the metal gate. The problem of dopant segregation caused by such manufacturing processes leads to a less controllable threshold voltage Vt of the device thus adversely affects the device performance.
Since the semiconductor power devices implemented with metal gate have lower gate resistance, several patent applications have disclosed semiconductor power devices implemented with various metal gates. In US Patent Application 20040137703 a MOSFET threshold voltage tuning is disclosed with metal gate stack control. The metal gate is formed with several metal layers with different thickness to control and tune the gate work functions. The method and device as disclosed however would not provide a solution to the dopant segregation problems.
In Patent Application 20040110097, a double gate semiconductor device with a metal gate is disclosed. The manufacturing method of the device includes the forming a gate structure over a channel portion of a fin structure. The method also includes a step of forming a sacrificial oxide layer around the gate structure and removing the gate structure to define a gate recess within the sacrificial oxide layer. AS metal gate is formed in the gate recess, and the sacrificial oxide layer is removed. In Patent Application 20020084486, a DMOS device is disclosed with metal gate. A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions are thus aligned to the gate, and the source diffusion provides a slight overlap for good turn-on characteristics and low leakage. The sacrificial gate layer is capable of withstanding the diffusion temperatures of the DMOS process and is selectively etchable. After the high-temperature processing is completed, the sacrificial gate layer is stripped and a gate metal is formed over the substrate, filling the volume left by the stripped sacrificial gate material. In another Patent Application 20020058374, a method of forming dual metal gates in the semiconductor device is disclosed. The method includes the formation of dummy gates in PMOS and NMOS areas and forming the interlayer insulation layer and subsequent processing steps of removing the interlayer insulation layer and the forming of grooves and the dual metal gates and the removal of the dummy gates. However, none of these methods provide practical and cost effective method to resolve the above-discussed problems.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the power devices such that the above discussed problems and limitations can be resolved.